1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which different types of field effect transistors are monolithically integrated.
2. Description of Related Art
Recent years technologies relating to semiconductor integrated circuits for mobile communication terminals have been progressing further. As performances of semiconductor integrated circuits for mobile communication terminals become higher, it is strongly demanded to monolithically integrate functional elements thereof.
By monolithically integrating functional elements, it is achieved to miniaturize the chip itself and to simplify bonding operation and so on.
Enhancement-mode FETs (field effect transistors) are used as power amplifier circuits for mobile communication terminals. This is because that it is required for power amplifier circuits to operate sharing a common power supply with other functional circuits. Meanwhile, depletion-mode FETs are used as switching circuits in mobile communication terminals. This is because that it is required for switching circuits to lower on-resistance thereof in order to realize low insertion loss.
Monolithic integration of enhancement-mode FETs and depletion-mode FETs is well known in the related art (Japanese Unexamined Patent Application Publication Nos. H07-142685, H06-216326, H06-326131, S61-59781 and Japanese Patent No. 2773700).
Depletion-mode FETs have a negative threshold voltage. Enhancement-mode FETs, on the other hand, have a positive threshold voltage. Therefore, it is required to set the threshold voltage different between the depletion-mode FET and the enhancement-mode FET.
FIG. 11 is a schematic diagram for explaining the technology described in Japanese Unexamined Patent Application Publication No. H07-142685. In FIG. 11, the distance between a gate electrode 1002 of an enhancement-mode FET to a channel layer 200 is shorter, by the thickness of an n-type GaAs layer 400, than the distance between a gate electrode 1004 of a depletion-mode FET to the channel layer 200. The difference between threshold voltages of the enhancement-mode FET and the depletion-mode FET is determined based on the difference in distance between the gate electrodes and channel layer. Japanese Unexamined Patent Application Publication Nos. H06-216326, H06-326131, S61-59781 and Japanese Patent No. 2773700 disclose the same technology as Japanese Unexamined Patent Application Publication No. H07-142685 above.
Japanese Unexamined Patent Application Publication No. S61-59781 discloses a semiconductor device in which a Schottky barrier-type FET, and a pn-junction-type FET which have the same junction depth and impurity concentration in channel regions are monolithically integrated.
It has now been discovered that using an enhancement-mode FET as a FET for a power amplifier circuit sufficiently reduces power consumption during non-operation of the power amplifier circuit, and hence that the threshold voltage may be set to a positive voltage greater than +0.3 V (more preferably, to a positive voltage greater than +0.4 V). Also, using a depletion-mode FET as a FET for a switching circuit allows sufficiently reducing insertion loss, and hence the threshold voltage may be set to a negative voltage greater than −0.5 V (more preferably, to a negative voltage greater than −0.6 V). The above settings result in a greater difference (differential voltage) between the threshold voltage of the enhancement-mode FET and the threshold voltage of the depletion-mode FET (more preferably, a differential voltage of 1V(=+0.4−(−0.6 V)).
In order to set such a large differential voltage, the gate-channel layer distance in the depletion-mode FET must be set to be sufficiently greater than the gate-channel layer distance in the enhancement-mode FET.
According to Japanese Unexamined Patent Application Publication No. H07-142685, the layer thickness of the above-described n-type GaAs layer 400 must be set to 50 nm. As the thickness of the GaAs layer becomes thicker, the gate of the enhancement-mode FET is to be arranged inside the semiconductor device. In this way, Electric fields converge in the gate, thereby decreasing the breakdown voltage of the gate. This precludes using such a FET as a FET for a power amplifier circuit in which a large voltage is applied to the gate. Even though providing a space on the side faces of the gate for increasing the breakdown voltage characteristics of the gate, it may result in decreased drain current and/or increased on-resistance.
In semiconductor devices having different types of FET monolithically integrated therein it is thus difficult to set optimal characteristics for each FET in accordance with the intended application.